(a) Field of the Invention
The present invention relates to a frequency multiplying system having a plurality of output frequencies and, more particularly, to a frequency multiplying system for generating a plurality of multiple-frequency signals based on an input reference-frequency signal.
(b) Description of the Related Art
A frequency multiplying system having a plurality of output frequencies is used in the field of computer systems for generating one or more multiple-frequency clocks having a frequency equal to or multiplied from a reference frequency of an input reference clock, the multiple frequency being generally 2n times as high as the reference frequency, where given n is an integer including zero. Such a frequency multiplying system, which may be called herein multiple-frequency clock generator, is generally implemented by a phase locked loop (PLL) circuit.
FIG. 12 shows the configuration of a conventional multiple-frequency clock generator or PLL circuit. The conventional PLL circuit 200 includes a frequency multiplier 201, a delay circuit 202, a phase comparator 203, and three frequency dividers 204, 205 and 206. The frequency multiplier 201 multiplies the reference frequency of an input reference clock CLK10 to generate an internal clock CLK20, which is fed through the delay circuit 202 to each of the frequency dividers 204, 205 and 206 while being introduced with a delay time.
Each frequency divider 204, 205 or 206 divides the delayed internal clock to generate a multiple-frequency clock having a specified multiple frequency. In this example, the frequency divider 204 generates a quadruple-frequency clock CLK14, the frequency divider 205 generates a double-frequency clock CLK12, and the frequency divider 206 generates an equal-frequency clock CLK11, wherein all these clocks having frequencies defined in terms of the reference frequency are output from the PLL circuit 200.
One of the output clocks CLK14, CLK12, CLK11 from the frequency dividers 204, 205 and 206 which has a period equal to or longer than the period of the reference frequency, namely the output clock CLK11 in this example, is fed-back as a feedback clock to the phase comparator 203 to form a feedback loop. The phase comparator 203 compares the phase of the feedback clock CLK11 against the phase of the reference clock CLK10 by using the rising edge of the reference clock CLK10, thereby determining the delay time to be effected by the delay circuit 202. The delay circuit 202 has a plurality of delay elements each for introducing a unit delay time, and determines a desired delay time by selecting a number of the delay elements. By introducing a suitable delay time to the multiple-frequency internal clock CLK20 in the delay circuit 202, the PLL circuit 200 is locked with the reference clock CLK10, wherein the multiple-frequency clocks CLK11, CLK12 and CLK13 are all in synchrony with the reference clock CLK10.
FIGS. 13A and 13B are timing charts (or waveform diagrams) showing the timing relationships between the reference clock CLK10 and the multiple-frequency clocks CLK11, CLK12 and CLK14, at the timing of the phase comparison (in FIG. 13A) and at the timing after the locking (in FIG. 13B). At the start for the locking operation, as shown in FIG. 13A, the feedback clock CLK15 lags by a time length t12 with respect to the reference clock CLK10 in terms of the rising edges of the reference clock CLK10 and the feedback clock CLK15. The phase comparator 203 controls the delay circuit 202 to introduce a desired delay time to the internal clock CLK20 so that the rising edge of the feedback clock CLK15 approaches the rising edge of the reference clock CLK10.
By iterating the phase comparison of both the rising edges and the delay control of the delay circuit 202 so as to introduce a suitable delay time to the internal clock CLK20, the phase comparator 203 allows the PLL circuit 200 to be locked with the reference clock CLK 10, after the delay time introduced by the delay circuit 202 equals a time length t22 to obtain a synchrony of both the rising edges. After the locking, the phases of the multiple-frequency clocks CLK11, CLK12 and CLK14 which are obtained by diving the internal clock CLK20 are in synchrony with the phase of reference clock CLK10, as shown in FIG. 13B.
It is to be noted that the achievement of locking by the PLL circuit 200 means that the phase difference between the reference clock CLK10 and the internal clock CLK20 resides within an allowable error range. More specifically, a more detailed comparison while enlarging the time axis would find a small phase difference corresponding to the error between both the clocks CLK10 and CLK20. In addition, there is also a small phase difference between each two of the multiple-frequency clocks CLK11, CLK 12 and CLK14 obtained by dividing the delayed internal clock. These small phase differences may cause a problem especially in the quadruple-frequency clock CLK14, although the small phase difference causes a substantially little problem in the equal-frequency clock CLK11, in view of the short period of the quadruple-frequency clock CLK14. In this respect, there is a possibility that the phase difference between the reference clock CLK10 and the quadruple-frequency clock CLK14 may be a sum of the maximum phase error between the reference clock CLK10 and the feedback clock CLK15 and the maximum phase error between the feedback clock CLK15 and the quadruple-frequency clock CLK14.
In the PLL circuit 200 of FIG. 12, the delay control range in the delay circuit 202 should correspond to the single period of the reference clock CLK10, and thus the delay circuit 202 includes a plurality of delay elements for introducing a delay of the delay control range corresponding to the single period of the reference clock CLK10. If the number of the delay elements in the delay circuit 202 is large, however, the delay circuit 202 has a corresponding large occupied area. In addition, if the reference clock CLK10 has a large period which corresponds to a plurality of unit delay times, a larger number of the delay elements further increase the occupied area of the delay circuit 202. Furthermore, a larger delay control range means that a larger locking time is needed in the PLL circuit 200.
If another of the multiple-frequency clocks CLK12 and CLK14 having a smaller period than the output clock CLK11 is employed as the feedback clock 15, the phase error may include only the phase difference between the another of the multiple-frequency clocks CLK 12 and CLK14 and the reference clock CLK10. FIGS. 14A and 14B show the timing charts, similarly to FIGS. 13A and 13B, respectively, in the case wherein the quadruple-frequency clock CLK14 is employed as the feedback clock CLK15.
It is assumed that the feedback clock CLK15 has a delay time t13 with respect to the reference clock CLK10, as shown in FIG. 14A, at the timing of the phase comparison, i.e., the start of the locking operation. After the phase comparison, a delay time is introduced to the feedback clock CLK15 so that the rising edge of the feedback clock CLK15 leading from and nearest to the rising edge of the reference clock CLK10 coincides with the rising edge of the reference clock CLK10. After a delay time corresponding to the time length t33 is introduced to the feedback clock CLK15, the PLL circuit 100 is locked with the reference clock CLK10. In this case, the delay control range corresponds to the period of the quadruple-frequency clock CLK14.
After the locking of the feedback clock CLK15 with the reference clock CLK10, however, the phase of the equal-frequency clock CLK11 deviates from the phase of the reference clock CLK10 by a half period in terms of the reference clock CLK10 although the multiple-frequency clocks CLK12 and CLK14 are in synchrony the reference clock CLK10, as shown in FIG. 14B.
More specifically, since the quadruple-frequency clock CLK14 having a shorter period than the reference clock CLK10 is employed as the feedback clock, there are four rising edges in the feedback clock corresponding to a single rising edge of the reference clock CLK10, any of the four rising edges of the feedback clock may coincide with the rising edge of the reference clock CLK10 after the locking to thereby cause a pseudo locking. That is, if a feedback clock has a shorter period than the reference clock CLK10, it is not assured that the phase of the other multiple-frequency clocks each having a longer period than the feedback clock coincides with the phase of the reference clock CLK10.
A technique is known which assures a safe locking for all the multiple-frequency clocks even if a feedback clock has a shorter period than the reference clock CLK10. In this technique, the first one of the clock pulses of the internal clock CLK20 in a single period of the reference clock CLK10 is delivered during the locking operation, without delivering the remaining clock pulses. FIGS. 15A and 15B show, similarly to FIGS. 13A and 13B, respectively, the timing charts of this technique. The situation is such that the PLL circuit 200 achieves a locking when a delay time t24 is introduced to the feedback clock CLK15, as understood from FIG. 15A. After the locking, all the clock pulses of the internal clock CLK20 in a single period of the reference clock CLK10 is delivered to generate the multiple-frequency clocks CLK14, CLK12 and CLK11, as shown in FIG. 15B.
In the technique shown in FIGS. 15A and 15B, all the multiple-frequency clocks CLK11, CLK12 and CLK14 can be synchronized with the reference clock CLK10, with a phase error including only the locking error between the feedback clock CLK15 and the reference clock CLK10. However, the delay circuit 202 must have delay elements in number corresponding to the single period of the reference clock CLK10. This increases the occupied area of the delay circuit 202 as mentioned before.
It is therefore an object of the present invention to provide a frequency multiplying system having a plurality of output frequencies, capable of synchronizing all the multiple-frequency clocks with the reference clock, having a delay step equal to one of the output clocks having a period shorter than the period of the reference clock, and achieving the locking with a smaller phase error.
The present invention provides a frequency multiplying system comprising: a frequency multiplier for multiplying a reference frequency of a reference clock by a specified number to generate an internal clock; a delay circuit for introducing a first variable delay to said internal clock to output a delayed internal clock; at least one clock generator for generating first clocks based on said delayed internal clock, said first clocks having a multiple of said reference frequency and consecutive phase shifts by an equal amount from a phase of said reference clock, said at least one clock generator selecting one of said first clocks having a phase leading from and nearest the phase of the reference clock, an output from one of said at least one clock generator being fed back as a feedback clock; and a first phase comparator for comparing a phase of said feedback clock against the phase of said reference clock, said first phase comparator controlling said first variable delay based on a result of comparison by said first phase comparator to achieve a locking.
In accordance with the frequency multiplying system of the present invention, a plurality of first clocks are generated having consecutive phase shifts from the phase of the reference clock, and one of the first clocks having a phase leading from and nearest to the reference clock is selected as the feedback clock for comparison in the phase comparator to achieve a locking. This allows a smaller delay control range compared to the conventional frequency multiplying system to reduce the locking time in the frequency multiplying system, without involving therein a pseudo locking.
It is to be noted that the term xe2x80x9cclockxe2x80x9d as used herein means a signal including a pulse train having a repetitive frequency, and that although the xe2x80x9cclockxe2x80x9d is typically used as a clock signal in a computer system etc., the xe2x80x9cclockxe2x80x9d in the present invention may be used other than as a clock signal so long as it includes a pulse train having a repetitive frequency.